COURSE OBJECTIVES
➢ To focus on the basic concept of VHDL and Verilog HDL
➢ To introduce the style of modeling in VHDL and Verilog HDL
➢ To focus advanced features of Verilog HDL
➢ To outline the formal procedures for testing and verification of HDL
➢ To introduce the design of high-level processors.
COURSE OUTCOMES
On completion of the course, student will be able to
CO1 - Develop VHDL and Verilog HDL codes for combinational logic circuits.
CO2 - Develop VHDL and Verilog HDL codes for sequential logic circuits.
CO3 - Analyze the computational complexity of various algorithms.
CO4 - Generate test bench for digital logic circuits.
CO5 - Implement various digital logic circuits by Moore and Mealey FSM.
CO6 - Implement various digital logic systems in FPGA’s.
- Teacher: Bhuvana B P
- Teacher: MUTHIAH M. A
- Teacher: MATHAN N
- Teacher: IMAYA S
- Teacher: RAVI T
- Teacher: VINO T
- Teacher: Balamurugan Velan